1. Field of the Invention
The present invention relates to an automatic gain control circuit and an automatic gain control method which are used for a circuit for controlling the amplitude of an input signal according to a multi-phase modulation method or a quadrature modulation method.
2. Description of Related Art
A device such as a personal computer composed of digital circuits has been recently widespread, and digital data is transmitted and received through a communication network. Also, in the communication service such as television broadcasting, to increase a utilization ratio of a limited usable frequency band, service based on the digital communication technology has been put to practical use. In this digital communication technology, the quadrature amplitude modulation (hereinafter, called QAM) is often used as one of digital modulation types.
In the QAM, a sine function and a cosine function orthogonal to each other are used, digital data is transformed into both amplitude information and phase information, and the amplitude information and the phase information are transmitted.
FIG. 6 is a graphic view showing the vector location of 16-point QAM in which four values are given to each of an in-phase signal and a quadrature signal. In FIG. 6, the I-axis indicates the amplitude of a cosine wave denoting an in-phase component, and the Q-axis indicates the amplitude of a sine wave denoting a quadrature component. Each signal point (hereinafter, called symbol) designated by a black point in FIG. 6 indicates a composite vector of both the sine wave and the cosine wave, the symbols denote discrete signals output at regular intervals, and each symbol has 4-bit information.
Also, the phase shift keying (hereafter, called PSK) is known as one of the digital modulation types. In this PSK, a sine function and a cosine function orthogonal to each other are used in the same manner as in the QAM, digital data is transformed into phase information, and the phase information is transmitted.
FIG. 7 is a graphic view showing the vector location of 8-phase PSK in which the phase of an in-phase signal and the phase of a quadrature signal are respectively divided into eight pieces. In FIG. 7, the I-axis indicates the amplitude of a cosine wave denoting an in-phase component, and the Q-axis indicates the amplitude of a sine wave denoting a quadrature component. Each signal point (hereinafter, called symbol) designated by a black point in FIG. 7 indicates a composite vector of both the sine wave and the cosine wave, the symbols denote discrete signals output at regular intervals, and each signal has 3-bit information.
In cases where the digital service is performed by using a wire transmission line such as a cable, distortion relating to the amplitude direction of a modulated signal hardly occurs in the wire transmission line. Therefore, the QAM is generally used for the communication service using the wire transmission line. In contrast, in case of the satellite communication using a radio transmission line, distortion relating to the amplitude direction of a modulated signal easily occurs due to characteristics of an amplifier placed at the relay point of a satellite. Therefore, the PSK is generally used for the communication service using the radio transmission line.
FIG. 8 is a constitutional view showing a general carrier wave reproducing system (hereinafter, called a demodulating system) for both a wave modulated according to the QAM and a wave modulated according to the PSK. In FIG. 8, 1 indicates a tuner for receiving a modulated signal modulated according to the QAM or PSK, 2 indicates a band pass filter, 3 indicates a gain changeable amplifier (hereinafter, called an AGC amplifier), 4 indicates an oscillator, 5 indicates a frequency changer, 6 indicates an analog-to-digital converter (hereinafter, called AID converter), and 7 indicates a carrier wave reproducing circuit (hereinafter, called a demodulating circuit).
An operation of the demodulating system will be described.
A high-frequency modulated signal such as a ground wave or a satellite wave transmitted through a wire transmission line or a radio transmission line is received in the tuner 1, and a high frequency of a transmission band in the modulated signal is changed in the tuner 1 to a constant frequency called an intermediate frequency ranging from 50 to 30 MHz.
Thereafter, noise existing out of the transmission band of the intermediate frequency is removed from the modulated signal in the band pass filter 2, the intermediate frequency of the modulated signal is changed to a low-band frequency in the frequency changer 5, and the modulated signal is input to the A/D converter 6. In the A/D converter 6, the analog modulated signal is converted into a digital modulated signal, and the digital modulated signal is input to the demodulating circuit 7. Thereafter, in the demodulating circuit 7, a digital process is performed for the input modulated signal to demodulate the input modulated signal to a demodulated signal, and digital data included in the demodulated signal is obtained.
In this case, to maintain a conversion precision in the A/D converter 6, the demodulating circuit 7 is required to maintain an average amplitude of the analog modulated signal input to the A/D converter 6. Therefore, an operation for maintaining a gain of the signal input to the A/D converter 6 is performed by the AGC amplifier 3 under the control of an AGC control signal output from an automatic gain control circuit of the demodulating circuit 7.
FIG. 9 is a constitutional view showing a general demodulating circuit. In FIG. 9, 11 indicates a multiplier, 12 indicates another multiplier, 13 indicates a low pass filter (hereinafter, called LPF), 14 indicates another low pass filter (hereinafter, called LPF), 28 indicates a conventional automatic gain control circuit, 15 indicates a de-rotator formed of a complex multiplier, 16 indicates a phase comparator, 17 indicates a loop filter, 18 indicates a numerical control oscillator (hereinafter, called NCO), 19 indicates a decoder, and 20 indicates an error correction circuit.
The input modulated signal input to a data input terminal of the demodulating circuit 7 is processed in digital circuits because the input modulated signal has been already converted into digital values in the A/D converter 6. The phase of the input modulated signal is detected in the multiplier 11 by using a local oscillating signal having a waveform of a cosine wave. Also, the phase of the input modulated signal is detected in the multiplier 12 by using a local oscillating signal having a waveform of a sine wave. Therefore, the input modulated signal is divided into in-phase components of symbols and quadrature components of the symbols. The in-phase component and the quadrature component of each symbol is orthogonal to each other. Here, each of the local oscillating signals respectively having a fixed frequency is output from a local oscillator. The in-phase components obtained in the multiplier 11 are input to the LPF 13, the quadrature components obtained in the multiplier 12 are input to the LPF 14, and the spectral reshaping is performed for the in-phase components and the quadrature components. Here, a frequency characteristic of the LPF 13 is the same as that of the LPF 14.
Each of the LPFs 13 and 14 is formed of a roll off filter or a root roll off filter in which a transfer characteristic required for the prevention of an inter-symbol interference in the digital data transmission is obtained. Therefore, in cases where the transfer characteristic is combined with a filter characteristic of a transmission end of the modulated signal, a raised cosine characteristic can be obtained to prevent the inter-symbol interference.
Both the in-phase component and the quadrature component of each symbol of the input modulated signal output from the LPFs 13 and 14 are input to the automatic gain control circuit 28. In the automatic gain control circuit 28, a power value of each symbol of the input modulated signal is calculated from information of the symbol, the calculated power value of each symbol is compared with a referential power value which corresponds to the modulation type adopted for the input modulated signal, and a difference between the power value of each symbol of the input modulated signal actually received and the referential power value is detected. Here, a referential power value corresponding to each of a plurality of modulation types is stored in advance in the automatic gain control circuit 28. Thereafter, an AGC control signal indicating the detected power differences of the symbols is output from the automatic gain control circuit 28 of the demodulating circuit 7 and is received in both an AGC amplifier arranged in the tuner 1 and the AGC amplifier 3. Therefore, the gain of the analog modulated signal input to the A/D converter 6 is maintained to a constant value according to the AGC control signal.
Also, the in-phase components and the quadrature components of the symbols of the input modulated signal output from the LPFs 13 and 14 are received in the de-rotator 15. Also, a data conversion digital signal SIN obtained from an analog sine signal and a data conversion digital signal COS obtained from an analog cosine signal are output from the NCO 18 and are received in the de-rotator 15. In the de-rotator 15, a phase shift and a frequency shift occurring between the in-phase components and the quadrature components of the input modulated signal are corrected.
Thereafter, the in-phase components and the quadrature components of the symbols corrected in the de-rotator 15 are received in both the decoder 19 and the phase comparator 16 as pieces of symbol information. In the decoder 19, the pieces of symbol information are converted into bit string data. In the phase comparator 16, an ideal phase of each symbol is predicted, and a difference between the ideal phase of the symbol and the phase of the symbol actually received is detected as a phase error for each symbol. Thereafter, each detected phase error is smoothed in the loop filter 17, and a digital signal indicating the smoothed phase errors is input to a frequency control terminal of the NCO 18. In the NCO 18, a signal having a frequency proportional to the frequency of the digital signal is produced. Also, the NCO 18 has a data converting function. Therefore, the data conversion signal SIN and the data conversion signal COS respectively having a frequency proportional to the frequency of the digital signal are output from the NCO 18 and are received in the de-rotator 15 as information used to correct both a phase shift and a frequency shift of the input modulated signal.
When both the phase shift and the frequency shift of the input modulated signal are removed from the output of the de-rotator 15, the bit string data output from the decoder 19 agrees with the digital data included in the modulated signal. Therefore, the modulated signal is demodulated to demodulated data, and the digital data is reproduced.
However, error is included in the demodulated data due to the influence of noise which occurs in dependence on environments of the transmission line. The relation between an amount of noise and a bit error rate of the demodulated data is theoretically determined for each modulation type. Because noise necessarily occurs in all types of transmission lines, the bit error necessarily occurs in the modulated signal transmitted through any type of transmission line.
Also, the data processing is performed for the demodulated data in latter stages of the demodulating system on the assumption that the modulated signal received is correctly demodulated to the bit string data. Therefore, in cases where bit error exists in the bit string data, even though a home page of an internet is, for example, opened, a picture registered in the home page is not displayed. To remove the bit error from the bit string data, the error correcting circuit 20 is arranged in the demodulating system.
Therefore, even though the bit string data output from the decoder 19 includes bit error, when a bit error rate of the bit error included in the bit string data is equal to or lower than an allowable error bit rate, the bit error included in the bit string data can be corrected in the error correcting circuit 20 so as to make the bit string data perfectly agree with the digital data output from a transmission end of the modulated signal. The error correcting circuit 20 is formed of a trellis decoder, a Viterbi decoder, a Read-Solomon decoder, or the combination of those decoders. Therefore, an output signal OUT of the error correcting circuit 20 denotes the output of the demodulating system.
FIG. 10 is a constitutional view showing the conventional automatic gain control circuit 28 arranged in the demodulating circuit 7.
In FIG. 10, 21 indicates a power calculating circuit for performing a square calculation for each piece of symbol information. 22 indicates a root calculating circuit for calculating a square root of a calculation result obtained in the power calculating circuit 21 as a power value of one symbol for each symbol. 23 indicates an adder for subtracting a reference value (hereinafter, called AGCR) from a power value of each symbol output from the root calculating circuit 22 and outputting a power difference for each symbol. The reference value expresses an ideal power value of the symbols relating to the corresponding modulation type, and a plurality of ideal power values are prescribed and stored for a plurality of modulation types in one-to-one correspondence. 24 indicates a multiplier for multiplying the power difference output from the adder 23 by a foxed gain (hereinafter, called AGCG) for each symbol. 25 indicates a loop filter for averaging a plurality of multiplication results of the multiplier 24. 26 indicates a pulse width modulator for producing the AGC control signal AGCPWM in which the output of the loop filter 25 is expressed by a pulse width.
Next, an operation of the conventional automatic gain control circuit 28 will be described.
Pieces of symbol information I of the in-phase components of the symbols and pieces of symbol information Q of the quadrature components of the symbols are output from the LPFs 13 and 14 and are received in the power calculating circuit 21. In the power calculating circuit 21, the piece of symbol information I of each in-phase component is squared to obtain a squared value I2, the piece of symbol information Q of each quadrature component is squared to obtain a squared value Q2, and the squared value I2 and the squared value Q2 are added together to obtain I2+Q2 for each symbol. Thereafter, the square root of the calculation result I2+Q2 of the power calculating circuit 21 is extracted in the root calculating circuit 22 for each symbol, and a power value √{square root over ( )}(I2+Q2) of each symbol is obtained. Here, the root calculating circuit 22 is generally formed of a read only memory.
Thereafter, the power value of each symbol is compared with the AGCR, which denotes a reference value expressing an ideal power value of the symbols and is prescribed for the corresponding modulation type, in the adder 23, and a difference between the power value and the AGCR is detected for each symbol. The AGCR is obtained by calculating an average of the power values of all symbols positioned according to an ideal symbol location of the symbols, so that the AGCR denotes an ideal power value. The value of the AGCR depends on the modulation type. Thereafter, the difference between the power value of each symbol and the AGCR denoting an ideal power value is multiplied by the AGCG denoting a fixed gain in the multiplier 24, and an average of multiplied values obtained in the multiplier 24 is calculated in the loop filter 25. The average value obtained in the loop filter 25 is changed to the AGC control signal AGCPWM having a direct current component in the pulse width modulator 26 (or a digital-to-analog converter not shown), and the direct current component of the AGC control signal is fed back to both the AGC amplifier 3 and an AGC amplifier of the tuner 1 so as to control the amplitude of the signal input to the A/D converter 6 to a constant value.
Next, another conventional automatic gain control circuit operated according to a peak power control method is described.
FIG. 11 is a constitutional view of another conventional automatic gain control circuit. In FIG. 11, 31 indicates a power calculating circuit, 32 indicates a threshold value counter, and 33 indicates a pulse width modulator. A peak power control method is often used in a demodulating system based on the PSK in which phase information is only used and the amplitude of a modulated signal, or a power value of each symbol, is always constant.
Pieces of symbol information I of the in-phase components of the symbols and pieces of symbol information Q of the quadrature components of the symbols are output from the LPFs 13 and 14 and are received in the power calculating circuit 31. In the power calculating circuit 31, the piece of symbol information I of each in-phase component is squared, the piece of symbol information Q of each quadrature component is squared, and the squared value I2 and the squared value Q2 are added together to obtain I2+Q2 for each symbol. Thereafter, the square root of the calculation result I2+Q2 of the power calculating circuit 31 is extracted in a root calculating circuit (not shown) for each symbol, a power value √{square root over ( )}(I2+Q2) of each symbol is obtained. Therefore, a power value of each symbol of the input modulated signal is calculated. In this case, in cases where the input modulated signal is produced according to the PSK, because the value I2+Q2 is constant, the calculation of the square root of the calculation result I2+Q2 in the root calculating circuit can be omitted.
Thereafter, in the threshold value counter 32, the number of symbols, of which the calculated power values are higher than a first threshold value obtained by adding a constant value to the ideal power value, is counted as a counted value during a predetermined time period, or the number of symbols, of which the calculated power values are lower than a second threshold value obtained by subtracting a constant value from the ideal power value, is counted as a counted value during a predetermined time period. The counted value is used to increase or decrease the amplitude of the modulated signal input to the A/D converter 6. In detail, the counted value of the threshold value counter 32 is changed to an AGC control signal AGCPWM having a direct current component in the pulse width modulator 33 (or a digital-to-analog converter not shown), and the direct current component of the AGC control signal is fed back to both the AGC amplifier 3 and an AGC amplifier of the tuner 1 so as to control the amplitude of the modulated signal input to the A/D converter 6 to a constant value.
Accordingly, the amplitude of the modulated signal input to the A/D converter 6 can be controlled by calculating a degree of control for both the AGC amplifier 3 and the AGC amplifier of the tuner 1 according to only the power information indicated by the symbol information I and Q.
However, there is probability that a large amount of noise is included in the input modulated signal, a reflected signal generated due to the mismatching of the transmission lines is superposed on the symbol information I and Q, and/or unnecessary radiation such as spurious radiation occurs in the transmission frequency band of the input modulated signal. In this case, because a power value of an unnecessary signal included in the symbol information I and Q is added to the power information indicated by the symbol information I and Q, the power value indicated by the symbol information I and Q cannot be correctly calculated. As a result, the amplitude of the modulated signal input to the A/D converter 6 becomes unstable so as to be out of the dynamic range of the A/D converter 6, the A/D conversion is not correctly performed in the A/D converter 6, the decoding in the decoder 19 of the demodulating circuit 7 is not correctly performed, and a bit error rate of the bit string data output from the decoder 19 becomes worse. Therefore, even though the modulated signal received in the tuner 1 includes a small amount of noise, there is probability that a bit error rate of the bit string data output from the decoder 19 exceeds the allowable error bit rate, and the bit error included in the bit string data cannot be perfectly corrected in the error correcting circuit 20. Accordingly, a problem has arisen that the demodulating system including the automatic gain control circuit is unstably operated.